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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><dl class="section note"><dt>Note</dt><dd><pre class="fragment">                                   User configurable parameters for PS eFUSE
   ---------------------------------------------------------------------------
   #define XSK_EFUSEPS_ENABLE_WRITE_PROTECT                                FALSE

   TRUE to burn the write protect bits in eFUSE array. Write protect
   has two bits, when any of the bit is blown, it is considered as write
   protected. So, while burning the Write protect bits, even if one bit is
   blown, write API returns success. Note that, POR reset is required after
   burning, for write protection of the eFUSE bits to come into effect.
   It is recommended to do the POR reset after write protection.
   Also note that, once write protect bits are burned, no more eFUSE writes
   are possible. So, please be sure when burning the write protect bits.
   If the Write protect macro is TRUE with other macros, write protect will
   be burned in the last, after burning all the defined values, so that for
   any error while burning other macros will not effect the total eFUSE array.
   FALSE will not modify the write protect bits.

   #define XSK_EFUSEPS_ENABLE_RSA_AUTH                                     FALSE

   TRUE to burn the RSA enable bit in PS eFUSE array. After enabling the bit,
   every successive boot must be RSA enabled apart from JTAG. Before burning
   this bit, make sure that eFUSE array has the valid PPK hash.If the PPK hash
   burning is enabled, only after writing the hash successfully, RSA enable
   bit will be blown. Note that, for RSA enable bit to take effect, POR reset
   is required.
   FALSE will not modify the RSA enable bit.

   #define XSK_EFUSEPS_ENABLE_ROM_128K_CRC                         FALSE
   TRUE will burn the ROM 128k crc bit. Every successive boot after this,
   BootROM will calculate 128k crc. FALSE will not modify the ROM CRC128K bit.

   #define XSK_EFUSEPS_DISABLE_DFT_JTAG            FALSE
   TRUE will disable DFT JTAG permanently.
   FALSE will not modify the eFuse PS DFT JTAG disable bit

   #define XSK_EFUSEPS_DISABLE_DFT_MODE            FALSE
   TRUE will disable DFT mode permanently.
   FALSE will not modify the eFuse PS DFT mode disable bit

   #define XSK_EFUSEPS_ENABLE_RSA_KEY_HASH                         FALSE
   TRUE will burn the eFUSE hash, that is given in XSK_EFUSEPS_RSA_KEY_HASH_VALUE
   when write API is used. TRUE will read the eFUSE hash when read API is used
   and will be read into structure. FALSE will ignore the value given.

   #define XSK_EFUSEPS_RSA_KEY_HASH_VALUE
                   "c8bb4d9e1fcdbd27b99d48a3df5720b98f35bafabb1e10333a78322fb82ce63d"

   The value mentioned in this will be converted to hex buffer and written
   into the PS eFUSE array when write API used. This value should be the
   PPK(Primary Public Key) hash given in string format. It should be 64
   characters long, valid characters are 0-9,a-f,A-F. Any other character
   is considered as invalid string and will not burn RSA hash.

   Note: When XilSKey_EfusePs_Write() API is used, above mentioned RSA hash
   is written and  XSK_EFUSEPS_ENABLE_RSA_KEY_HASH should have TRUE value.

                           User configurable parameters for PL eFUSE for Zynq
   -----------------------------------------------------------------------
   #define         XSK_EFUSEPL_FORCE_PCYCLE_RECONFIG                       FALSE
   TRUE then part has to be power cycled to be able to be reconfigured.
   FALSE will not set the eFUSE control bit.

   #define         XSK_EFUSEPL_DISABLE_KEY_WRITE                           FALSE
   TRUE will disable eFUSE write to FUSE_AES and FUSE_USER blocks
   XFLASE will enable eFUSE write to FUSE_AES and FUSE_USER blocks

   #define         XSK_EFUSEPL_DISABLE_AES_KEY_READ                        FALSE
   TRUE will disable the write to FUSE_AES &amp; FUSE_USER key &amp; disables
   read of FUSE_AES.
   FALSE will enable eFUSE read from &amp; write to FUSE_AES and FUSE_USER blocks

   #define         XSK_EFUSEPL_DISABLE_USER_KEY_READ                       FALSE
   TRUE will disable the write to FUSE_AES &amp; FUSE_USER key &amp; disables read of
   FUSE_USER
   FALSE will enable eFUSE read from &amp; write to FUSE_AES and FUSE_USER blocks

   Note: If any one of the above two definitions are FALSE then reading of
   FUSE_AES &amp; FUSE_USER is not possible

   #define         XSK_EFUSEPL_DISABLE_FUSE_CNTRL_WRITE            FALSE
   TRUE will disable the eFUSE write to FUSE_CTRL block
   FALSE will not set the eFUSE control bit, so that user can write into
   FUSE_CTRL block later.

   #define         XSK_EFUSEPL_FORCE_USE_AES_ONLY                          FALSE
   TRUE will force to use secure boot with eFUSE AES key only
   FALSE will not set the eFUSE control bit so that user can use non-secure
   boot.

   #define         XSK_EFUSEPL_DISABLE_JTAG_CHAIN                          FALSE
   If TRUE then permanently sets the Zynq ARM DAP controller in bypass mode.
   FALSE will allow Zynq ARM DAP visible through JTAG.

   #define         XSK_EFUSEPL_BBRAM_KEY_DISABLE                           FALSE
   TRUE will force eFUSE key to be used if booting Secure Image.
   FALSE will not set the eFUSE control bit so that user can use secure boot
   with BBRAM key.

   Following are the MIO pins used for PL JTAG operations.
   User can change these pins as their discretion.
   #define         XSK_EFUSEPL_MIO_JTAG_TDI                                (17)
   #define         XSK_EFUSEPL_MIO_JTAG_TDO                                (21)
   #define         XSK_EFUSEPL_MIO_JTAG_TCK                                (19)
   #define         XSK_EFUSEPL_MIO_JTAG_TMS                                (20)

   MUX selection pin:
   #define         XSK_EFUSEPL_MIO_JTAG_MUX_SELECT         (11)
   This pin is used to select between the external JTAG or MIO driving JTAG
   operations.

   #define         XSK_EFUSEPL_MIO_MUX_SEL_DEFAULT_VAL                             LOW
   LOW writes zero on the mux select line before writing the PL eFUSE
   HIGH writes one on the mux select line before writing the PL eFUSE

   #define XSK_EFUSEPL_PROGRAM_AES_AND_USER_LOW_KEY                FALSE
   TRUE will burn the AES &amp; User Low hash key, that is given in
   XSK_EFUSEPL_AES_KEY &amp; XSK_EFUSEPL_USER_LOW_KEY respectively.
   FALSE will ignore the values given.

   Note: User cannot write AES Key &amp; User Low Key separately.

   #define XSK_EFUSEPL_PROGRAM_USER_HIGH_KEY                               FALSE
   TRUE will burn the User High hash key, that is given in
   XSK_EFUSEPL_AES_KEY &amp; XSK_EFUSEPL_USER_LOW_KEY respectively.
   FALSE will ignore the values given.

   #define         XSK_EFUSEPL_AES_KEY
           "0000000000000000000000000000000000000000000000000000000000000000"
   The value mentioned in this will be converted to hex buffer and written
   into the PL eFUSE array when write API used. This value should be the
   AES key given in string format. It should be 64
   characters long, valid characters are 0-9,a-f,A-F. Any other character
   is considered as invalid string and will not burn AES Key. Note that,
   for writing the AES Key, XSK_EFUSEPL_PROGRAM_AES_AND_USER_LOW_KEY should
   have TRUE value.

   #define         XSK_EFUSEPL_USER_LOW_KEY                        "00"
   The value mentioned in this will be converted to hex buffer and written
   into the PL eFUSE array when write API used. This value should be the
   User Low Key given in string format. It should be 2 characters long, valid
    characters are 0-9,a-f,A-F. Any other character is considered as invalid
    string and will not burn User Low Key. Note that, for writing the AES Key,
    XSK_EFUSEPL_PROGRAM_AES_AND_USER_LOW_KEY should have TRUE value.


   #define         XSK_EFUSEPL_USER_HIGH_KEY                       "000000"
   The value mentioned in this will be converted to hex buffer and written
   into the PL eFUSE array when write API used. This value should be the User
    High Key given in string format. It should be 6 characters long, valid
    characters are 0-9,a-f,A-F. Any other character is considered as invalid
    string and will not burn User High Key. Note that, for writing the AES
    Key, XSK_EFUSEPL_PROGRAM_USER_HIGH_KEY should have TRUE value.
</pre></dd></dl>
<h2>BBRAM related definitions: </h2>
<p>MIO pins used for JTAG signals. Can be changed as per hardware. #define XSK_BBRAM_MIO_JTAG_TDI (17) #define XSK_BBRAM_MIO_JTAG_TDO (21) #define XSK_BBRAM_MIO_JTAG_TCK (19) #define XSK_BBRAM_MIO_JTAG_TMS (20) #define XSK_BBRAM_MIO_JTAG_MUX_SELECT (11) #define XSK_BBRAM_MIO_MUX_SEL_DEFAULT_VAL LOW Default value to enable the PL JTAG This is the 256 bit key to be programmed into BBRAM. This should entered by user in HEX. #define XSK_BBRAM_AES_KEY "349de4571ae6d88de23de65489acf67000ff5ec901ae3d409aabbce4549812dd" #define XSK_BBRAM_AES_KEY_SIZE_IN_BITS 256 </p>
<pre class="fragment">   User configurable parameters for PL eFUSE for Kintex Ultrascale
   -----------------------------------------------------------------------
   #define XSK_EFUSEPL_PGM_SLR_CONFIG_ORDER_0      FALSE
   #define XSK_EFUSEPL_PGM_SLR_CONFIG_ORDER_1      FALSE
   #define XSK_EFUSEPL_PGM_SLR_CONFIG_ORDER_2      FALSE
   #define XSK_EFUSEPL_PGM_SLR_CONFIG_ORDER_3      FALSE
   TRUE will select particular SLR(1/2/3/4) to program:
   - AES Keys(256bits/SLR)
   - User Fuse bits (32bits/SLR)
   - User Keys (128bits/SLR)
   - RSA Public Key HASH (384bits/SLR)
   FALSE will disable programming.

   #define XSK_EFUSEPL_DISABLE_AES_KEY_READ        FALSE
   TRUE will permanently disables the write to FUSE_AES and
   check CRC for AES key by programming control bit of FUSE.
   FALSE will not modify this control bit of eFuse.

   #define XSK_EFUSEPL_DISABLE_USER_KEY_READ       FALSE
   TRUE will permanently disables the write to 32 bit FUSE_USER and
   read of FUSE_USER key by programming control bit of FUSE.
   FALSE will not modify this control bit of eFuse.

   #define XSK_EFUSEPL_DISABLE_SECURE_READ         FALSE
   TRUE will permanently disables the write to FUSE_Secure block
   and reading of secure block by programming control bit of FUSE.
   FALSE will not modify this control bit of eFuse.

   #define XSK_EFUSEPL_DISABLE_FUSE_CNTRL_WRITE    FALSE
   TRUE will permanently disables the write to FUSE_CNTRL block
   by programming control bit of FUSE.
   FALSE will not modify this control bit of eFuse.

   #define XSK_EFUSEPL_DISABLE_RSA_KEY_READ        FALSE
   TRUE will permanently disables the write to FUSE_RSA block and
   reading of FUSE_RSA Hash by programming control bit of FUSE.
   FALSE will not modify this control bit of eFuse.

   #define XSK_EFUSEPL_DISABLE_KEY_WRITE           FALSE
   TRUE will permanently disables the write to FUSE_AES block by
   programming control bit of FUSE.
   FALSE will not modify this control bit of eFuse.

   #define XSK_EFUSEPL_DISABLE_USER_KEY_WRITE      FALSE
   TRUE will permanently disables the write to FUSE_USER block
   by programming control bit of FUSE.
   FALSE will not modify this control bit of eFuse.

   #define XSK_EFUSEPL_DISABLE_SECURE_WRITE        FALSE
   TRUE will permanently disables the write to FUSE_SECURE block
   by programming control bit of FUSE.
   FALSE will not modify this control bit of eFuse.

   #define XSK_EFUSEPL_DISABLE_RSA_HASH_WRITE      FALSE
   TRUE will permanently disables the write to FUSE_RSA authentication
   key by programming control bit of FUSE.
   FALSE will not modify this control bit of eFuse.

   #define XSK_EFUSEPL_DISABLE_128BIT_USER_KEY_WRITE       FALSE
   TRUE will permanently disables the write to 128 bit FUSE_USER
   by programming control bit of FUSE.
   FALSE will not modify this control bit of eFuse

   #define XSK_EFUSEPL_ALLOW_ENCRYPTED_ONLY        FALSE
   TRUE will permanently allows encrypted bitstream only.
   FALSE will not modify this Secure bit of eFuse.

   #define XSK_EFUSEPL_FORCE_USE_FUSE_AES_ONLY     FALSE
   TRUE then allows only FUSE's AES key as source of encryption
   FALSE then allows FPGA to configure an unencrypted bitstream or
   bitstream encrypted using key stored BBRAM or eFuse.

   #define XSK_EFUSEPL_ENABLE_RSA_AUTH             FALSE
   TRUE will enable RSA authentication of bitstream
   FALSE will not modify this secure bit of eFuse.

   #define XSK_EFUSEPL_DISABLE_JTAG_CHAIN          FALSE
   TRUE will disable JTAG permanently.
   FALSE will not modify this secure bit of eFuse.

   #define XSK_EFUSEPL_DISABLE_TEST_ACCESS         FALSE
   TRUE will disables Xilinx test access.
   FALSE will not modify this secure bit of eFuse.

   #define XSK_EFUSEPL_DISABLE_AES_DECRYPTOR       FALSE
   TRUE will disables decoder completely.
   FALSE will not modify this secure bit of eFuse.

   #define XSK_EFUSEPL_ENABLE_OBFUSCATION_EFUSEAES FALSE
   TRUE will enable obfuscation feature for eFUSE AES key,
   this instructs the device to decode the eFUSE AES key
   to actual AES key before decrypting the bitstream.
   FALSE will not modify this secure bit of eFUSE.

  #define XSK_EFUSEPL_AXI_GPIO_DEVICE_ID  XPAR_AXI_GPIO_0_DEVICE_ID
  Default value is XPAR_AXI_GPIO_0_DEVICE_ID
  This macro is for providing exact GPIO device ID, based on the
  design configuration this macro should be modified to provide
  GPIO device ID which is used for connecting MASTER JTAG pins.

   In Ultrascale GPIO pins used for connecting MASTER_JTAG pins and
   hardware module to access eFUSE.
   Following are the GPIO pins and user can change these pins
   #define XSK_EFUSEPL_AXI_GPIO_JTAG_TDO   (0)
   #define XSK_EFUSEPL_AXI_GPIO_HWM_READY  (1)
   #define XSK_EFUSEPL_AXI_GPIO_HWM_END    (2)

   #define XSK_EFUSEPL_AXI_GPIO_JTAG_TDI   (0)
   #define XSK_EFUSEPL_AXI_GPIO_JTAG_TMS   (1)
   #define XSK_EFUSEPL_AXI_GPIO_JTAG_TCK   (2)
   #define XSK_EFUSEPL_AXI_GPIO_HWM_START  (3)

   #define XSK_EFUSEPL_GPIO_INPUT_CH                       (2)
   This macro is for providing channel number of ALL INPUTS connected
   (Master JTAG's - TDO, Hardware module's - READY and END)
   #define XSK_EFUSEPL_GPIO_OUTPUT_CH                      (1)
   This macro is for providing channel number of ALL OUTPUTS connected
   (Master JTAG's - TDI, TCK, TMS,and Hardware module's - START)

   NOTE: All inputs and outputs of GPIO can be configured in single
   channel also
   i.e XSK_EFUSEPL_GPIO_INPUT_CH = XSK_EFUSEPL_GPIO_OUTPUT_CH = 1 or 2.
   Among (TDI, TCK, TMS, START) Outputs of GPIO cannot be connected to
   different GPIO channels all the 4 signals should be in same channel.
   (TDO, READY and END) can be a other channel of (TDI, TCK, TMS, START)
   or the same.

   #define XSK_EFUSEPL_PROGRAM_AES_KEY             FALSE
   TRUE will burn the AES key given in XSK_EFUSEPL_AES_KEY.
   FALSE will ignore the values given.

   #define XSK_EFUSEPL_PROGRAM_USER_KEY    FALSE
   TRUE will burn 32 bit User key given in XSK_EFUSEPL_USER_KEY
   FALSE will ignore the values given.

   #define XSK_EFUSEPL_PROGRAM_RSA_HASH    FALSE
   TRUE will burn RSA hash given in XSK_EFUSEPL_RSA_KEY_HASH_VALUE
   FALSE will ignore the values given.

   #define XSK_EFUSEPL_PROGRAM_USER_KEY_128BIT     FALSE
   TRUE will burn 128 bit User key given in XSK_EFUSEPL_USER_KEY_128BIT_CONFIG_ORDER_0,
   XSK_EFUSEPL_USER_KEY_128BIT_CONFIG_ORDER_1, XSK_EFUSEPL_USER_KEY_128BIT_CONFIG_ORDER_2,
   XSK_EFUSEPL_USER_KEY_128BIT_CONFIG_ORDER_3
   FALSE will ignore the values given.

   #define XSK_EFUSEPL_CHECK_AES_KEY               FALSE
   TRUE will perform CRC check of FUSE_AES with provided CRC value in macro
   XSK_EFUSEPL_CRC_OF_EXPECTED_AES_KEY.
   And result of CRC check will be updated in XilSKey_EPl instance
   parameter AESKeyMatched with either TRUE or FALSE.
   FALSE CRC check of FUSE_AES will not be performed.

   #define XSK_EFUSEPL_READ_USER_KEY               FALSE
   TRUE will read 32 bit FUSE_USER from Ultrascale's eFuse and updates in
   XilSKey_EPl instance parameter UserKeyReadback
   FALSE 32 bit FUSE_USER key read will not be performed.

   #define XSK_EFUSEPL_READ_RSA_HASH               FALSE
   TRUE will read FUSE_USER from Ultrascale's eFuse and updates in
   XilSKey_EPl instance parameter RSAHashReadback
   FALSE FUSE_RSA_HASH read will not be performed.

   #define XSK_EFUSEPL_READ_USER_KEY128_BIT        FALSE
   TRUE will read 128 bit USER key from Ultrascale's eFuse and updates in
   XilSKey_EPl instance parameter User128BitReadBack
   FALSE 128 bit USER key read will not be performed.

   #define XSK_EFUSEPL_AES_KEY_CONFIG_ORDER_0
   "0000000000000000000000000000000000000000000000000000000000000000"
   #define XSK_EFUSEPL_AES_KEY_CONFIG_ORDER_1
   "0000000000000000000000000000000000000000000000000000000000000000"
   #define XSK_EFUSEPL_AES_KEY_CONFIG_ORDER_2
   "0000000000000000000000000000000000000000000000000000000000000000"
   #define XSK_EFUSEPL_AES_KEY_CONFIG_ORDER_3
   "0000000000000000000000000000000000000000000000000000000000000000"
   The value mentioned in this will be converted to hex buffer and written
   into the PL eFUSE array when write API used. This value should be the
   AES key given in string format. It should be 64
   characters long, valid characters are 0-9,a-f,A-F. Any other character
   is considered as invalid string and will not burn AES Key. Note that,
   for writing the AES Key, XSK_EFUSEPL_PROGRAM_AES_KEY for
   particular SLR(1/2/3/4)should have TRUE value.

   #define XSK_EFUSEPL_USER_KEY_CONFIG_ORDER_0     "00000000"
   #define XSK_EFUSEPL_USER_KEY_CONFIG_ORDER_1     "00000000"
   #define XSK_EFUSEPL_USER_KEY_CONFIG_ORDER_2     "00000000"
   #define XSK_EFUSEPL_USER_KEY_CONFIG_ORDER_3             "00000000"
   The value mentioned in this will be converted to hex buffer and written
   into the PL eFUSE array when write API used. This value should be the
   User Key given in string format. It should be 8 characters long, valid
   characters are 0-9,a-f,A-F. Any other character is considered as invalid
   string and will not burn User Key. Note that, for writing the User Key,
   XSK_EFUSEPL_PROGRAM_USER_KEY_ULTRA for particular SLR(1/2/3/4)should
   have TRUE value.

   #define XSK_EFUSEPL_RSA_KEY_HASH_VALUE_CONFIG_ORDER_0
           "0000000000000000000000000000000000000000000000 \
           00000000000000000000000000000000000000000000000000"
   #define XSK_EFUSEPL_RSA_KEY_HASH_VALUE_CONFIG_ORDER_1
           "0000000000000000000000000000000000000000000000  \
           00000000000000000000000000000000000000000000000000"
   #define XSK_EFUSEPL_RSA_KEY_HASH_VALUE_CONFIG_ORDER_2
           "0000000000000000000000000000000000000000000000  \
           00000000000000000000000000000000000000000000000000"
   #define XSK_EFUSEPL_RSA_KEY_HASH_VALUE_CONFIG_ORDER_3
           "0000000000000000000000000000000000000000000000  \
           00000000000000000000000000000000000000000000000000"
   The value mentioned in this will be converted to hex buffer and written
   into the PL eFUSE array when write API used. This value should be the
   RSA Key hash given in string format. It should be 96 characters long,
   valid characters are 0-9,a-f,A-F. Any other character is considered as
   invalid string and will not burn RSA hash value. Note that, for writing
   the RSA hash, XSK_EFUSEPL_PROGRAM_RSA_HASH_ULTRA for particular SLR(1/2/3/4)
   should have TRUE value.

   #define XSK_EFUSEPL_USER_KEY_128BIT_0_CONFIG_ORDER_0    "00000000"
   #define XSK_EFUSEPL_USER_KEY_128BIT_1_CONFIG_ORDER_0    "00000000"
   #define XSK_EFUSEPL_USER_KEY_128BIT_2_CONFIG_ORDER_0    "00000000"
   #define XSK_EFUSEPL_USER_KEY_128BIT_3_CONFIG_ORDER_0    "00000000"

   #define XSK_EFUSEPL_USER_KEY_128BIT_0_CONFIG_ORDER_1    "00000000"
   #define XSK_EFUSEPL_USER_KEY_128BIT_1_CONFIG_ORDER_1    "00000000"
   #define XSK_EFUSEPL_USER_KEY_128BIT_2_CONFIG_ORDER_1    "00000000"
   #define XSK_EFUSEPL_USER_KEY_128BIT_3_CONFIG_ORDER_1    "00000000"

   #define XSK_EFUSEPL_USER_KEY_128BIT_0_CONFIG_ORDER_2    "00000000"
   #define XSK_EFUSEPL_USER_KEY_128BIT_1_CONFIG_ORDER_2    "00000000"
   #define XSK_EFUSEPL_USER_KEY_128BIT_2_CONFIG_ORDER_2    "00000000"
   #define XSK_EFUSEPL_USER_KEY_128BIT_3_CONFIG_ORDER_2    "00000000"

   #define XSK_EFUSEPL_USER_KEY_128BIT_0_CONFIG_ORDER_3    "00000000"
   #define XSK_EFUSEPL_USER_KEY_128BIT_1_CONFIG_ORDER_3    "00000000"
   #define XSK_EFUSEPL_USER_KEY_128BIT_2_CONFIG_ORDER_3    "00000000"
   #define XSK_EFUSEPL_USER_KEY_128BIT_3_CONFIG_ORDER_3    "00000000"
   The above four macros are meant for providing 128 bit User key for SLR(1/2/3/4),
   XSK_EFUSEPL_USER_KEY_128BIT_CONFIG_ORDER_0 holds 31:0 bits,
   XSK_EFUSEPL_USER_KEY_128BIT_CONFIG_ORDER_1 holds 63:32 bits,
   XSK_EFUSEPL_USER_KEY_128BIT_CONFIG_ORDER_2 holds 95:64 bits and
   XSK_EFUSEPL_USER_KEY_128BIT_CONFIG_ORDER_3 holds 127:96 bits of whole 128 bit User
   key.
   The value mentioned in this will be converted to hex buffer and written
   into the PL eFUSE array when write API used. This value should be the
   User Key given in string format. It should be 8 characters long, valid
   characters are 0-9,a-f,A-F. Any other character is considered as invalid
   string and will not burn User Key. Note that, for writing the User Key,
   XSK_EFUSEPL_PROGRAM_USER_KEY_128BIT should have TRUE value.

   #define XSK_EFUSEPL_CRC_OF_EXPECTED_AES_KEY_CONFIG_ORDER_0
   XSK_EFUSEPL_AES_CRC_OF_ALL_ZEROS
</pre><p> #define XSK_EFUSEPL_CRC_OF_EXPECTED_AES_KEY_CONFIG_ORDER_1 XSK_EFUSEPL_AES_CRC_OF_ALL_ZEROS #define XSK_EFUSEPL_CRC_OF_EXPECTED_AES_KEY_CONFIG_ORDER_2 XSK_EFUSEPL_AES_CRC_OF_ALL_ZEROS #define XSK_EFUSEPL_CRC_OF_EXPECTED_AES_KEY_CONFIG_ORDER_3 XSK_EFUSEPL_AES_CRC_OF_ALL_ZEROS</p>
<p>XSK_EFUSEPL_AES_CRC_OF_ALL_ZEROS is the default value for all SLRs and is hexadecimal CRC value of FUSE_AES with all Zeros. Please provide CRC of the AES key programmed. For Checking CRC of FUSE_AES XSK_EFUSEPL_CHECK_AES_KEY_ULTRA macro should be TRUE otherwise CRC check will not be performed. For calculation of AES key's CRC one can use u32 XilSKey_CrcCalculation(u8 *Key) API</p>
<p>NOTE:Please make sure you have sufficient heap and stack to run this application. For more information on creating vivado design please refer to xapp1283.</p>
<pre>
 MODIFICATION HISTORY:</pre><pre> Ver   Who      Date     Changes
</p>
<hr/>
<p>
 1.00a rpoolla 04/26/13 First release
 1.01a hk      09/18/13 Added BBRAM related definitions
 3.00  vns     31/07/15 Added efuse functionality for Ultrascale.
                        In Ultrascale GPIO pins and channels macros are added
                        to access Master Jtag primitive and also added
                        extra control bits and secure bits for Ultrascale's
                        eFuse.
 4.00  vns     09/10/15 Added DFT JTAG disable and DFT MODE disable programming
                        options for Zynq eFuse PS.
 6.0   vns     07/07/16 Added Gpio pin numbers connected to hardware module.
               27/08/16 Modified XSK_EFUSEPL_DISABLE_DECODER macro to
                        XSK_EFUSEPL_DISABLE_AES_DECRYPTOR
 6.1   vns     10/25/16 Removed XSK_BBRAM_FORCE_PCYCLE_RECONFIG and
                        XSK_BBRAM_DISABLE_JTAG_CHAIN, from Zynq BBRAM
                        configurations as they are not actually
                        programming any control bit. These 2 are part of the
                        eFUSE PL and they already exist at eFUSE PL
                        configurations (XSK_EFUSEPL_FORCE_PCYCLE_RECONFIG and
                        XSK_EFUSEPL_DISABLE_JTAG_CHAIN)
 6.4   vns     02/27/18 Added support for programming secure bit -
                        enable obfuscation feature for eFUSE AES key
 6.7   psl     03/20/19 Added eFuse key write support for SSIT devices.
       psl     03/29/19 Added support for user configurable GPIO for
                        jtag control.
 6.8   psl     05/28/19 Added Macro for expected CRC of AES key for different
                        SLR.
 6.8   psl     06/07/19 Added doxygen tags.
 7.5   ng      07/13/23 added SDT support
 7.6   vss     04/08/25 Corrected efuse AXI GPIO device ID macro name.
 </pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ab811d8c6ff3a505312d3276590444289"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#ab811d8c6ff3a505312d3276590444289">LOW</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ab811d8c6ff3a505312d3276590444289"><td class="mdescLeft">&#160;</td><td class="mdescRight">Voltage level definitions.  <a href="#ab811d8c6ff3a505312d3276590444289">More...</a><br/></td></tr>
<tr class="separator:ab811d8c6ff3a505312d3276590444289"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9dc2b1efc06cb416f47f666cb928ce95"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a9dc2b1efc06cb416f47f666cb928ce95">XSK_EFUSEPL_PGM_SLR_CONFIG_ORDER_0</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a9dc2b1efc06cb416f47f666cb928ce95"><td class="mdescLeft">&#160;</td><td class="mdescRight"><h2>Definition of Zynq PL </h2>
 <a href="#a9dc2b1efc06cb416f47f666cb928ce95">More...</a><br/></td></tr>
<tr class="separator:a9dc2b1efc06cb416f47f666cb928ce95"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a32a7550d4b349f396975c7bbf47c9753"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a32a7550d4b349f396975c7bbf47c9753">XSK_EFUSEPL_DISABLE_AES_KEY_READ</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a32a7550d4b349f396975c7bbf47c9753"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following is the define to select if the user wants to program control bits.  <a href="#a32a7550d4b349f396975c7bbf47c9753">More...</a><br/></td></tr>
<tr class="separator:a32a7550d4b349f396975c7bbf47c9753"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a69eb8d7b978503f8e2df800619fa2e1c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a69eb8d7b978503f8e2df800619fa2e1c">XSK_EFUSEPL_DISABLE_USER_KEY_READ</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a69eb8d7b978503f8e2df800619fa2e1c"><td class="mdescLeft">&#160;</td><td class="mdescRight">If TRUE will disable 32 bit User key reading and programming.  <a href="#a69eb8d7b978503f8e2df800619fa2e1c">More...</a><br/></td></tr>
<tr class="separator:a69eb8d7b978503f8e2df800619fa2e1c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6d36a04bc5d165c0ec921b71b06b4cc8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a6d36a04bc5d165c0ec921b71b06b4cc8">XSK_EFUSEPL_DISABLE_SECURE_READ</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a6d36a04bc5d165c0ec921b71b06b4cc8"><td class="mdescLeft">&#160;</td><td class="mdescRight">If TRUE will disable secure block reading and programming.  <a href="#a6d36a04bc5d165c0ec921b71b06b4cc8">More...</a><br/></td></tr>
<tr class="separator:a6d36a04bc5d165c0ec921b71b06b4cc8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a24ecfdedb5cfeb51d4a0eb46b7665326"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a24ecfdedb5cfeb51d4a0eb46b7665326">XSK_EFUSEPL_DISABLE_FUSE_CNTRL_WRITE</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a24ecfdedb5cfeb51d4a0eb46b7665326"><td class="mdescLeft">&#160;</td><td class="mdescRight">If TRUE will disable programming control bits.  <a href="#a24ecfdedb5cfeb51d4a0eb46b7665326">More...</a><br/></td></tr>
<tr class="separator:a24ecfdedb5cfeb51d4a0eb46b7665326"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9e6f29fbe2ae5d0a8888d8babd33ceea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a9e6f29fbe2ae5d0a8888d8babd33ceea">XSK_EFUSEPL_DISABLE_RSA_KEY_READ</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a9e6f29fbe2ae5d0a8888d8babd33ceea"><td class="mdescLeft">&#160;</td><td class="mdescRight">If TRUE will disable RSA key hash reading and programming.  <a href="#a9e6f29fbe2ae5d0a8888d8babd33ceea">More...</a><br/></td></tr>
<tr class="separator:a9e6f29fbe2ae5d0a8888d8babd33ceea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9f4256a60fd63c50992aa5417b001a53"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a9f4256a60fd63c50992aa5417b001a53">XSK_EFUSEPL_DISABLE_KEY_WRITE</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a9f4256a60fd63c50992aa5417b001a53"><td class="mdescLeft">&#160;</td><td class="mdescRight">If TRUE will disable AES key programming.  <a href="#a9f4256a60fd63c50992aa5417b001a53">More...</a><br/></td></tr>
<tr class="separator:a9f4256a60fd63c50992aa5417b001a53"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac077850702136e793b4eebeb68789ee0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#ac077850702136e793b4eebeb68789ee0">XSK_EFUSEPL_DISABLE_USER_KEY_WRITE</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:ac077850702136e793b4eebeb68789ee0"><td class="mdescLeft">&#160;</td><td class="mdescRight">If TRUE will disable Programming 32 bit User key.  <a href="#ac077850702136e793b4eebeb68789ee0">More...</a><br/></td></tr>
<tr class="separator:ac077850702136e793b4eebeb68789ee0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aec67e43b447466ee30afe3e3e843f14f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#aec67e43b447466ee30afe3e3e843f14f">XSK_EFUSEPL_DISABLE_SECURE_WRITE</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:aec67e43b447466ee30afe3e3e843f14f"><td class="mdescLeft">&#160;</td><td class="mdescRight">If TRUE will disable programming Secure block.  <a href="#aec67e43b447466ee30afe3e3e843f14f">More...</a><br/></td></tr>
<tr class="separator:aec67e43b447466ee30afe3e3e843f14f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1fe8e326d51a14890d3613a8de33ca97"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a1fe8e326d51a14890d3613a8de33ca97">XSK_EFUSEPL_DISABLE_RSA_HASH_WRITE</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a1fe8e326d51a14890d3613a8de33ca97"><td class="mdescLeft">&#160;</td><td class="mdescRight">If TRUE will disable programming to RSA key hash.  <a href="#a1fe8e326d51a14890d3613a8de33ca97">More...</a><br/></td></tr>
<tr class="separator:a1fe8e326d51a14890d3613a8de33ca97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa45b6ddf0ea61824f5ce88825bb17fae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#aa45b6ddf0ea61824f5ce88825bb17fae">XSK_EFUSEPL_DISABLE_128BIT_USER_KEY_WRITE</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:aa45b6ddf0ea61824f5ce88825bb17fae"><td class="mdescLeft">&#160;</td><td class="mdescRight">If TRUE will disable Programming 128 bit User key.  <a href="#aa45b6ddf0ea61824f5ce88825bb17fae">More...</a><br/></td></tr>
<tr class="separator:aa45b6ddf0ea61824f5ce88825bb17fae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac923fc8de09b3b8bad7f06c48aa04e70"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#ac923fc8de09b3b8bad7f06c48aa04e70">XSK_EFUSEPL_ALLOW_ENCRYPTED_ONLY</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:ac923fc8de09b3b8bad7f06c48aa04e70"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following is the define to select if the user wants to program Secure bits.  <a href="#ac923fc8de09b3b8bad7f06c48aa04e70">More...</a><br/></td></tr>
<tr class="separator:ac923fc8de09b3b8bad7f06c48aa04e70"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad14bece75c983e61cf1d11f5765c0d44"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#ad14bece75c983e61cf1d11f5765c0d44">XSK_EFUSEPL_FORCE_USE_FUSE_AES_ONLY</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:ad14bece75c983e61cf1d11f5765c0d44"><td class="mdescLeft">&#160;</td><td class="mdescRight">If TRUE will force to use Secure boot with eFUSE key only.  <a href="#ad14bece75c983e61cf1d11f5765c0d44">More...</a><br/></td></tr>
<tr class="separator:ad14bece75c983e61cf1d11f5765c0d44"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6199ced282f260e182e7252a78354551"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a6199ced282f260e182e7252a78354551">XSK_EFUSEPL_ENABLE_RSA_AUTH</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a6199ced282f260e182e7252a78354551"><td class="mdescLeft">&#160;</td><td class="mdescRight">If TRUE will enable RSA authentication of bitstream.  <a href="#a6199ced282f260e182e7252a78354551">More...</a><br/></td></tr>
<tr class="separator:a6199ced282f260e182e7252a78354551"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a71b64715838c481f02f08c0500e6e8c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a71b64715838c481f02f08c0500e6e8c3">XSK_EFUSEPL_DISABLE_JTAG_CHAIN</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a71b64715838c481f02f08c0500e6e8c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">If TRUE then permanently sets the Ultrascale device in bypass mode.  <a href="#a71b64715838c481f02f08c0500e6e8c3">More...</a><br/></td></tr>
<tr class="separator:a71b64715838c481f02f08c0500e6e8c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2cf32a008decb67551ce6d3928e9b8a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a2cf32a008decb67551ce6d3928e9b8a6">XSK_EFUSEPL_DISABLE_TEST_ACCESS</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a2cf32a008decb67551ce6d3928e9b8a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">If TRUE will disable internal test access for ULTRASCALE.  <a href="#a2cf32a008decb67551ce6d3928e9b8a6">More...</a><br/></td></tr>
<tr class="separator:a2cf32a008decb67551ce6d3928e9b8a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3c22cfe79258da35575529ac9c5a2fed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a3c22cfe79258da35575529ac9c5a2fed">XSK_EFUSEPL_DISABLE_AES_DECRYPTOR</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a3c22cfe79258da35575529ac9c5a2fed"><td class="mdescLeft">&#160;</td><td class="mdescRight">If TRUE will Disable AES decryptor.  <a href="#a3c22cfe79258da35575529ac9c5a2fed">More...</a><br/></td></tr>
<tr class="separator:a3c22cfe79258da35575529ac9c5a2fed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a856a6d64b6f7bae8f125b3206b984f92"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a856a6d64b6f7bae8f125b3206b984f92">XSK_EFUSEPL_ENABLE_OBFUSCATION_EFUSEAES</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a856a6d64b6f7bae8f125b3206b984f92"><td class="mdescLeft">&#160;</td><td class="mdescRight">If TRUE will enable obfuscation feature for eFUSE's AES key.  <a href="#a856a6d64b6f7bae8f125b3206b984f92">More...</a><br/></td></tr>
<tr class="separator:a856a6d64b6f7bae8f125b3206b984f92"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a52ee2396e79f7348aa8129ae832f407e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a52ee2396e79f7348aa8129ae832f407e">XSK_EFUSEPL_AXI_GPIO_DEVICE_ID</a>&#160;&#160;&#160;XPAR_AXI_GPIO_0_DEVICE_ID</td></tr>
<tr class="memdesc:a52ee2396e79f7348aa8129ae832f407e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following defines should be given in decimal/hexa-decimal values.  <a href="#a52ee2396e79f7348aa8129ae832f407e">More...</a><br/></td></tr>
<tr class="separator:a52ee2396e79f7348aa8129ae832f407e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab07d64f1a24bac9013d128decded32a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#ab07d64f1a24bac9013d128decded32a3">XSK_EFUSEPL_AXI_GPIO_JTAG_TDO</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ab07d64f1a24bac9013d128decded32a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASTER JTAG GPIO pin for TDO.  <a href="#ab07d64f1a24bac9013d128decded32a3">More...</a><br/></td></tr>
<tr class="separator:ab07d64f1a24bac9013d128decded32a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3e5671abdf541887baa675db2cb647ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a3e5671abdf541887baa675db2cb647ab">XSK_EFUSEPL_AXI_GPIO_HWM_READY</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:a3e5671abdf541887baa675db2cb647ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tells whether hardware module is ready or not.  <a href="#a3e5671abdf541887baa675db2cb647ab">More...</a><br/></td></tr>
<tr class="separator:a3e5671abdf541887baa675db2cb647ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4b46859387bf852a331f3b9d335496f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a4b46859387bf852a331f3b9d335496f6">XSK_EFUSEPL_AXI_GPIO_HWM_END</a>&#160;&#160;&#160;(2)</td></tr>
<tr class="memdesc:a4b46859387bf852a331f3b9d335496f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Notifies hardware module programming completion.  <a href="#a4b46859387bf852a331f3b9d335496f6">More...</a><br/></td></tr>
<tr class="separator:a4b46859387bf852a331f3b9d335496f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acd8b2e9d1221ea136d85ec0ff732c004"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#acd8b2e9d1221ea136d85ec0ff732c004">XSK_EFUSEPL_AXI_GPIO_JTAG_TDI</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:acd8b2e9d1221ea136d85ec0ff732c004"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASTER JTAG GPIO pin for TDI.  <a href="#acd8b2e9d1221ea136d85ec0ff732c004">More...</a><br/></td></tr>
<tr class="separator:acd8b2e9d1221ea136d85ec0ff732c004"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6d1a6e92268be8777cb047b602dad96a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a6d1a6e92268be8777cb047b602dad96a">XSK_EFUSEPL_AXI_GPIO_JTAG_TMS</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:a6d1a6e92268be8777cb047b602dad96a"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASTER JTAG GPIO pin for TMS.  <a href="#a6d1a6e92268be8777cb047b602dad96a">More...</a><br/></td></tr>
<tr class="separator:a6d1a6e92268be8777cb047b602dad96a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeb60bdc7ee93e8271fdf9d4c2b371637"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#aeb60bdc7ee93e8271fdf9d4c2b371637">XSK_EFUSEPL_AXI_GPIO_JTAG_TCK</a>&#160;&#160;&#160;(2)</td></tr>
<tr class="memdesc:aeb60bdc7ee93e8271fdf9d4c2b371637"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASTER JTAG GPIO pin for TCK.  <a href="#aeb60bdc7ee93e8271fdf9d4c2b371637">More...</a><br/></td></tr>
<tr class="separator:aeb60bdc7ee93e8271fdf9d4c2b371637"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3313ad0856dd592234aa55030acdd050"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a3313ad0856dd592234aa55030acdd050">XSK_EFUSEPL_AXI_GPIO_HWM_START</a>&#160;&#160;&#160;(3)</td></tr>
<tr class="memdesc:a3313ad0856dd592234aa55030acdd050"><td class="mdescLeft">&#160;</td><td class="mdescRight">Triggers Hardware module, for programming start.  <a href="#a3313ad0856dd592234aa55030acdd050">More...</a><br/></td></tr>
<tr class="separator:a3313ad0856dd592234aa55030acdd050"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9a81580dacc2270f0daaed8aae100750"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a9a81580dacc2270f0daaed8aae100750">XSK_EFUSEPL_GPIO_INPUT_CH</a>&#160;&#160;&#160;(2)</td></tr>
<tr class="memdesc:a9a81580dacc2270f0daaed8aae100750"><td class="mdescLeft">&#160;</td><td class="mdescRight">GPIO Channel for which TDO, Hardware module ready and end pins connected.  <a href="#a9a81580dacc2270f0daaed8aae100750">More...</a><br/></td></tr>
<tr class="separator:a9a81580dacc2270f0daaed8aae100750"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a82e4c58666c3f5f1f08b6588f468702d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a82e4c58666c3f5f1f08b6588f468702d">XSK_EFUSEPL_GPIO_OUTPUT_CH</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:a82e4c58666c3f5f1f08b6588f468702d"><td class="mdescLeft">&#160;</td><td class="mdescRight">GPIO Channel for which Hardware module Starte, TDI,.  <a href="#a82e4c58666c3f5f1f08b6588f468702d">More...</a><br/></td></tr>
<tr class="separator:a82e4c58666c3f5f1f08b6588f468702d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a13ad3c35e580ea044b38e632b35708ee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a13ad3c35e580ea044b38e632b35708ee">XSK_EFUSEPL_PROGRAM_AES_KEY</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a13ad3c35e580ea044b38e632b35708ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following is the define to select if the user wants to select AES, User, RSA and RES keys for Ultrascale.  <a href="#a13ad3c35e580ea044b38e632b35708ee">More...</a><br/></td></tr>
<tr class="separator:a13ad3c35e580ea044b38e632b35708ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afcc335e078dd3033a2c58dfc6a2b5e7a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#afcc335e078dd3033a2c58dfc6a2b5e7a">XSK_EFUSEPL_PROGRAM_USER_KEY</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:afcc335e078dd3033a2c58dfc6a2b5e7a"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRUE burns the USER key.  <a href="#afcc335e078dd3033a2c58dfc6a2b5e7a">More...</a><br/></td></tr>
<tr class="separator:afcc335e078dd3033a2c58dfc6a2b5e7a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8407a268cde433bd3c30dd84bbbba17c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a8407a268cde433bd3c30dd84bbbba17c">XSK_EFUSEPL_PROGRAM_RSA_KEY_HASH</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a8407a268cde433bd3c30dd84bbbba17c"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRUE burns the RSA hash.  <a href="#a8407a268cde433bd3c30dd84bbbba17c">More...</a><br/></td></tr>
<tr class="separator:a8407a268cde433bd3c30dd84bbbba17c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3352ec7a859c58c3702d1d0bada54f20"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a3352ec7a859c58c3702d1d0bada54f20">XSK_EFUSEPL_PROGRAM_USER_KEY_128BIT</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a3352ec7a859c58c3702d1d0bada54f20"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRUE burns 128 bit USER key.  <a href="#a3352ec7a859c58c3702d1d0bada54f20">More...</a><br/></td></tr>
<tr class="separator:a3352ec7a859c58c3702d1d0bada54f20"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae046eedb98b0ca25cfcf00f398c1e854"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#ae046eedb98b0ca25cfcf00f398c1e854">XSK_EFUSEPL_CHECK_AES_KEY_CRC</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:ae046eedb98b0ca25cfcf00f398c1e854"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRUE checks AES key with below provided CRC.  <a href="#ae046eedb98b0ca25cfcf00f398c1e854">More...</a><br/></td></tr>
<tr class="separator:ae046eedb98b0ca25cfcf00f398c1e854"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a347b687cbd4844cc6b43d2b9137614dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a347b687cbd4844cc6b43d2b9137614dc">XSK_EFUSEPL_READ_USER_KEY</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a347b687cbd4844cc6b43d2b9137614dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRUE read 32 bit USER key.  <a href="#a347b687cbd4844cc6b43d2b9137614dc">More...</a><br/></td></tr>
<tr class="separator:a347b687cbd4844cc6b43d2b9137614dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abe87a9c44421a207d99847a3a2fe9681"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#abe87a9c44421a207d99847a3a2fe9681">XSK_EFUSEPL_READ_RSA_KEY_HASH</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:abe87a9c44421a207d99847a3a2fe9681"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRUE read RSA Hash value.  <a href="#abe87a9c44421a207d99847a3a2fe9681">More...</a><br/></td></tr>
<tr class="separator:abe87a9c44421a207d99847a3a2fe9681"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7330b5e6185ce49f678bd124191851af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a7330b5e6185ce49f678bd124191851af">XSK_EFUSEPL_READ_USER_KEY128_BIT</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a7330b5e6185ce49f678bd124191851af"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRUE reads 128 bit USER key.  <a href="#a7330b5e6185ce49f678bd124191851af">More...</a><br/></td></tr>
<tr class="separator:a7330b5e6185ce49f678bd124191851af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8b39f907fe8aef2d27f92ed7fbf172ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a8b39f907fe8aef2d27f92ed7fbf172ad">XSK_EFUSEPL_AES_KEY_CONFIG_ORDER_0</a>&#160;&#160;&#160;&quot;0000000000000000000000000000000000000000000000000000000000000000&quot;</td></tr>
<tr class="memdesc:a8b39f907fe8aef2d27f92ed7fbf172ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following defines should be given in the form of hex string.  <a href="#a8b39f907fe8aef2d27f92ed7fbf172ad">More...</a><br/></td></tr>
<tr class="separator:a8b39f907fe8aef2d27f92ed7fbf172ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2da041527f9e60608313d0ed3230c0b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a2da041527f9e60608313d0ed3230c0b8">XSK_EFUSEPL_RSA_KEY_HASH_VALUE_CONFIG_ORDER_0</a>&#160;&#160;&#160;&quot;000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000&quot;</td></tr>
<tr class="memdesc:a2da041527f9e60608313d0ed3230c0b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following defines should be given only for Ultrascale the length of RSA string must be 96.  <a href="#a2da041527f9e60608313d0ed3230c0b8">More...</a><br/></td></tr>
<tr class="separator:a2da041527f9e60608313d0ed3230c0b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7ea41e599d2f384830c7fd718dfa0113"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a7ea41e599d2f384830c7fd718dfa0113">XSK_EFUSEPL_USER_KEY_128BIT_0_CONFIG_ORDER_0</a>&#160;&#160;&#160;&quot;00000000&quot;	/* 31:0 */</td></tr>
<tr class="memdesc:a7ea41e599d2f384830c7fd718dfa0113"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following define should be given only for Ultrascale the total length of User 128-bit register is 128bit, to make it easier 128 bit register is broken into four 32 bit, single bit programming is also available.  <a href="#a7ea41e599d2f384830c7fd718dfa0113">More...</a><br/></td></tr>
<tr class="separator:a7ea41e599d2f384830c7fd718dfa0113"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2a87752a585cdc5031b13131abe68085"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a2a87752a585cdc5031b13131abe68085">XSK_EFUSEPL_CRC_OF_EXPECTED_AES_KEY_CONFIG_ORDER_0</a>&#160;&#160;&#160;XSK_EFUSEPL_AES_CRC_OF_ALL_ZEROS</td></tr>
<tr class="memdesc:a2a87752a585cdc5031b13131abe68085"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following define is CRC value of expected AES key.  <a href="#a2a87752a585cdc5031b13131abe68085">More...</a><br/></td></tr>
<tr class="separator:a2a87752a585cdc5031b13131abe68085"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3889f2adc0f009d96515da1a00fa71eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a3889f2adc0f009d96515da1a00fa71eb">XSK_EFUSEPS_ENABLE_WRITE_PROTECT</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a3889f2adc0f009d96515da1a00fa71eb"><td class="mdescLeft">&#160;</td><td class="mdescRight"><h2>Similarly we can define PS eFUSE related data </h2>
 <a href="#a3889f2adc0f009d96515da1a00fa71eb">More...</a><br/></td></tr>
<tr class="separator:a3889f2adc0f009d96515da1a00fa71eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afe8e63a4e7e38867ee26c0bbc98a9d13"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#afe8e63a4e7e38867ee26c0bbc98a9d13">XSK_EFUSEPS_ENABLE_RSA_AUTH</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:afe8e63a4e7e38867ee26c0bbc98a9d13"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the RSA Authentication eFUSE Bit.  <a href="#afe8e63a4e7e38867ee26c0bbc98a9d13">More...</a><br/></td></tr>
<tr class="separator:afe8e63a4e7e38867ee26c0bbc98a9d13"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae6e646b55e445adaac2932f9e3472fc3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#ae6e646b55e445adaac2932f9e3472fc3">XSK_EFUSEPS_ENABLE_ROM_128K_CRC</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:ae6e646b55e445adaac2932f9e3472fc3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the ROM code 128K crc eFUSE Bit.  <a href="#ae6e646b55e445adaac2932f9e3472fc3">More...</a><br/></td></tr>
<tr class="separator:ae6e646b55e445adaac2932f9e3472fc3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ade1acea86c1f8fc273d692290b65d5c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#ade1acea86c1f8fc273d692290b65d5c8">XSK_EFUSEPS_DISABLE_DFT_JTAG</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:ade1acea86c1f8fc273d692290b65d5c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">DFT jtag Disable.  <a href="#ade1acea86c1f8fc273d692290b65d5c8">More...</a><br/></td></tr>
<tr class="separator:ade1acea86c1f8fc273d692290b65d5c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4c3f1935c4f3a4d845e2b908b0b4a35c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a4c3f1935c4f3a4d845e2b908b0b4a35c">XSK_EFUSEPS_DISABLE_DFT_MODE</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a4c3f1935c4f3a4d845e2b908b0b4a35c"><td class="mdescLeft">&#160;</td><td class="mdescRight">DFT mode Disable.  <a href="#a4c3f1935c4f3a4d845e2b908b0b4a35c">More...</a><br/></td></tr>
<tr class="separator:a4c3f1935c4f3a4d845e2b908b0b4a35c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a50d686024989f6b036d043335c66469c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a50d686024989f6b036d043335c66469c">XSK_EFUSEPS_ENABLE_RSA_KEY_HASH</a>&#160;&#160;&#160;FALSE</td></tr>
<tr class="memdesc:a50d686024989f6b036d043335c66469c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enabling this RsaKeyHashValue[64] is written to eFUSE array.  <a href="#a50d686024989f6b036d043335c66469c">More...</a><br/></td></tr>
<tr class="separator:a50d686024989f6b036d043335c66469c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8ac2d516599594a2e245fd3260517fac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a8ac2d516599594a2e245fd3260517fac">XSK_BBRAM_MIO_JTAG_TDI</a>&#160;&#160;&#160;(17)</td></tr>
<tr class="memdesc:a8ac2d516599594a2e245fd3260517fac"><td class="mdescLeft">&#160;</td><td class="mdescRight">JTAG MIO pin for TDI.  <a href="#a8ac2d516599594a2e245fd3260517fac">More...</a><br/></td></tr>
<tr class="separator:a8ac2d516599594a2e245fd3260517fac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a855df416e26b9d6e82a6b1fd7bed3838"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a855df416e26b9d6e82a6b1fd7bed3838">XSK_BBRAM_MIO_JTAG_TDO</a>&#160;&#160;&#160;(21)</td></tr>
<tr class="memdesc:a855df416e26b9d6e82a6b1fd7bed3838"><td class="mdescLeft">&#160;</td><td class="mdescRight">JTAG MIO pin for TDO.  <a href="#a855df416e26b9d6e82a6b1fd7bed3838">More...</a><br/></td></tr>
<tr class="separator:a855df416e26b9d6e82a6b1fd7bed3838"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a185ba8a1bbbe3dce6facb5c7e3add24f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a185ba8a1bbbe3dce6facb5c7e3add24f">XSK_BBRAM_MIO_JTAG_TCK</a>&#160;&#160;&#160;(19)</td></tr>
<tr class="memdesc:a185ba8a1bbbe3dce6facb5c7e3add24f"><td class="mdescLeft">&#160;</td><td class="mdescRight">JTAG MIO pin for TCK.  <a href="#a185ba8a1bbbe3dce6facb5c7e3add24f">More...</a><br/></td></tr>
<tr class="separator:a185ba8a1bbbe3dce6facb5c7e3add24f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0ef1e832969a454349d7ed62d82e88b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a0ef1e832969a454349d7ed62d82e88b1">XSK_BBRAM_MIO_JTAG_TMS</a>&#160;&#160;&#160;(20)</td></tr>
<tr class="memdesc:a0ef1e832969a454349d7ed62d82e88b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">JTAG MIO pin for TMS.  <a href="#a0ef1e832969a454349d7ed62d82e88b1">More...</a><br/></td></tr>
<tr class="separator:a0ef1e832969a454349d7ed62d82e88b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a752dcf195942b7d9a7d4e01d01e2b7fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a752dcf195942b7d9a7d4e01d01e2b7fe">XSK_BBRAM_MIO_JTAG_MUX_SELECT</a>&#160;&#160;&#160;(11)</td></tr>
<tr class="memdesc:a752dcf195942b7d9a7d4e01d01e2b7fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">JTAG MIO pin for MUX selection line.  <a href="#a752dcf195942b7d9a7d4e01d01e2b7fe">More...</a><br/></td></tr>
<tr class="separator:a752dcf195942b7d9a7d4e01d01e2b7fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5b69a281922edbcc3706b4a7f9843d00"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__input_8h.html#a5b69a281922edbcc3706b4a7f9843d00">XSK_BBRAM_AES_KEY</a>&#160;&#160;&#160;&quot;349de4571ae6d88de23de65489acf67000ff5ec901ae3d409aabbce4549812dd&quot;</td></tr>
<tr class="memdesc:a5b69a281922edbcc3706b4a7f9843d00"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is the 256 bit key to be programmed into BBRAM.  <a href="#a5b69a281922edbcc3706b4a7f9843d00">More...</a><br/></td></tr>
<tr class="separator:a5b69a281922edbcc3706b4a7f9843d00"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ab811d8c6ff3a505312d3276590444289"></a>
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          <td class="memname">#define LOW&#160;&#160;&#160;0</td>
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<p>Voltage level definitions. </p>

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<a class="anchor" id="a5b69a281922edbcc3706b4a7f9843d00"></a>
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          <td class="memname">#define XSK_BBRAM_AES_KEY&#160;&#160;&#160;&quot;349de4571ae6d88de23de65489acf67000ff5ec901ae3d409aabbce4549812dd&quot;</td>
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<p>This is the 256 bit key to be programmed into BBRAM. </p>
<p>This should entered by user in HEX. </p>

<p>Referenced by <a class="el" href="xilskey__bbram__example_8c.html#aa2a34496cba738813e2c992e8d15a260">XilSKey_Bbram_InitData()</a>.</p>

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<a class="anchor" id="a752dcf195942b7d9a7d4e01d01e2b7fe"></a>
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          <td class="memname">#define XSK_BBRAM_MIO_JTAG_MUX_SELECT&#160;&#160;&#160;(11)</td>
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<p>JTAG MIO pin for MUX selection line. </p>
<p>Default value to enable the PL JTAG </p>

<p>Referenced by <a class="el" href="xilskey__bbram__example_8c.html#aa2a34496cba738813e2c992e8d15a260">XilSKey_Bbram_InitData()</a>.</p>

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          <td class="memname">#define XSK_BBRAM_MIO_JTAG_TCK&#160;&#160;&#160;(19)</td>
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<p>JTAG MIO pin for TCK. </p>

<p>Referenced by <a class="el" href="xilskey__bbram__example_8c.html#aa2a34496cba738813e2c992e8d15a260">XilSKey_Bbram_InitData()</a>.</p>

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          <td class="memname">#define XSK_BBRAM_MIO_JTAG_TDI&#160;&#160;&#160;(17)</td>
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<p>JTAG MIO pin for TDI. </p>

<p>Referenced by <a class="el" href="xilskey__bbram__example_8c.html#aa2a34496cba738813e2c992e8d15a260">XilSKey_Bbram_InitData()</a>.</p>

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          <td class="memname">#define XSK_BBRAM_MIO_JTAG_TDO&#160;&#160;&#160;(21)</td>
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<p>JTAG MIO pin for TDO. </p>

<p>Referenced by <a class="el" href="xilskey__bbram__example_8c.html#aa2a34496cba738813e2c992e8d15a260">XilSKey_Bbram_InitData()</a>.</p>

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          <td class="memname">#define XSK_BBRAM_MIO_JTAG_TMS&#160;&#160;&#160;(20)</td>
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<p>JTAG MIO pin for TMS. </p>

<p>Referenced by <a class="el" href="xilskey__bbram__example_8c.html#aa2a34496cba738813e2c992e8d15a260">XilSKey_Bbram_InitData()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPL_AES_KEY_CONFIG_ORDER_0&#160;&#160;&#160;&quot;0000000000000000000000000000000000000000000000000000000000000000&quot;</td>
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<p>Following defines should be given in the form of hex string. </p>
<p>The length of AES_KEY string must me 64 and for 32 bit USER_KEY must be 8. </p>

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          <td class="memname">#define XSK_EFUSEPL_ALLOW_ENCRYPTED_ONLY&#160;&#160;&#160;FALSE</td>
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<p>Following is the define to select if the user wants to program Secure bits. </p>
<p>If TRUE will force to use only encrypted bitstreams </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a52ee2396e79f7348aa8129ae832f407e"></a>
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          <td class="memname">#define XSK_EFUSEPL_AXI_GPIO_DEVICE_ID&#160;&#160;&#160;XPAR_AXI_GPIO_0_DEVICE_ID</td>
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<p>Following defines should be given in decimal/hexa-decimal values. </p>
<p>These are to be defined for Ultrascale Microblaze AXI GPIO pin numbers connected to MASTER JTAG primitive and corresponding channel numbers for GPIO pins </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a4b46859387bf852a331f3b9d335496f6"></a>
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          <td class="memname">#define XSK_EFUSEPL_AXI_GPIO_HWM_END&#160;&#160;&#160;(2)</td>
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<p>Notifies hardware module programming completion. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPL_AXI_GPIO_HWM_READY&#160;&#160;&#160;(1)</td>
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<p>Tells whether hardware module is ready or not. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPL_AXI_GPIO_HWM_START&#160;&#160;&#160;(3)</td>
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<p>Triggers Hardware module, for programming start. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="aeb60bdc7ee93e8271fdf9d4c2b371637"></a>
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          <td class="memname">#define XSK_EFUSEPL_AXI_GPIO_JTAG_TCK&#160;&#160;&#160;(2)</td>
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<p>MASTER JTAG GPIO pin for TCK. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="acd8b2e9d1221ea136d85ec0ff732c004"></a>
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          <td class="memname">#define XSK_EFUSEPL_AXI_GPIO_JTAG_TDI&#160;&#160;&#160;(0)</td>
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<p>MASTER JTAG GPIO pin for TDI. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="ab07d64f1a24bac9013d128decded32a3"></a>
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          <td class="memname">#define XSK_EFUSEPL_AXI_GPIO_JTAG_TDO&#160;&#160;&#160;(0)</td>
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<p>MASTER JTAG GPIO pin for TDO. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a6d1a6e92268be8777cb047b602dad96a"></a>
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          <td class="memname">#define XSK_EFUSEPL_AXI_GPIO_JTAG_TMS&#160;&#160;&#160;(1)</td>
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<p>MASTER JTAG GPIO pin for TMS. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="ae046eedb98b0ca25cfcf00f398c1e854"></a>
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          <td class="memname">#define XSK_EFUSEPL_CHECK_AES_KEY_CRC&#160;&#160;&#160;FALSE</td>
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<p>TRUE checks AES key with below provided CRC. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a4ea026a1ab321b06be36cf1cb5192148">XilSKey_EfusePl_ReadnCheck()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPL_CRC_OF_EXPECTED_AES_KEY_CONFIG_ORDER_0&#160;&#160;&#160;XSK_EFUSEPL_AES_CRC_OF_ALL_ZEROS</td>
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<p>Following define is CRC value of expected AES key. </p>

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          <td class="memname">#define XSK_EFUSEPL_DISABLE_128BIT_USER_KEY_WRITE&#160;&#160;&#160;FALSE</td>
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<p>If TRUE will disable Programming 128 bit User key. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a3c22cfe79258da35575529ac9c5a2fed"></a>
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          <td class="memname">#define XSK_EFUSEPL_DISABLE_AES_DECRYPTOR&#160;&#160;&#160;FALSE</td>
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<p>If TRUE will Disable AES decryptor. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a32a7550d4b349f396975c7bbf47c9753"></a>
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          <td class="memname">#define XSK_EFUSEPL_DISABLE_AES_KEY_READ&#160;&#160;&#160;FALSE</td>
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<p>Following is the define to select if the user wants to program control bits. </p>
<p>If TRUE will disable AES key crc check andprogramming </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a24ecfdedb5cfeb51d4a0eb46b7665326"></a>
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          <td class="memname">#define XSK_EFUSEPL_DISABLE_FUSE_CNTRL_WRITE&#160;&#160;&#160;FALSE</td>
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<p>If TRUE will disable programming control bits. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a71b64715838c481f02f08c0500e6e8c3"></a>
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          <td class="memname">#define XSK_EFUSEPL_DISABLE_JTAG_CHAIN&#160;&#160;&#160;FALSE</td>
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<p>If TRUE then permanently sets the Ultrascale device in bypass mode. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a9f4256a60fd63c50992aa5417b001a53"></a>
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          <td class="memname">#define XSK_EFUSEPL_DISABLE_KEY_WRITE&#160;&#160;&#160;FALSE</td>
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<p>If TRUE will disable AES key programming. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a1fe8e326d51a14890d3613a8de33ca97"></a>
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          <td class="memname">#define XSK_EFUSEPL_DISABLE_RSA_HASH_WRITE&#160;&#160;&#160;FALSE</td>
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<p>If TRUE will disable programming to RSA key hash. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a9e6f29fbe2ae5d0a8888d8babd33ceea"></a>
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<p>If TRUE will disable RSA key hash reading and programming. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a6d36a04bc5d165c0ec921b71b06b4cc8"></a>
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          <td class="memname">#define XSK_EFUSEPL_DISABLE_SECURE_READ&#160;&#160;&#160;FALSE</td>
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<p>If TRUE will disable secure block reading and programming. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="aec67e43b447466ee30afe3e3e843f14f"></a>
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          <td class="memname">#define XSK_EFUSEPL_DISABLE_SECURE_WRITE&#160;&#160;&#160;FALSE</td>
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<p>If TRUE will disable programming Secure block. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a2cf32a008decb67551ce6d3928e9b8a6"></a>
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<p>If TRUE will disable internal test access for ULTRASCALE. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a69eb8d7b978503f8e2df800619fa2e1c"></a>
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<p>If TRUE will disable 32 bit User key reading and programming. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="ac077850702136e793b4eebeb68789ee0"></a>
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<p>If TRUE will disable Programming 32 bit User key. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a856a6d64b6f7bae8f125b3206b984f92"></a>
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          <td class="memname">#define XSK_EFUSEPL_ENABLE_OBFUSCATION_EFUSEAES&#160;&#160;&#160;FALSE</td>
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<p>If TRUE will enable obfuscation feature for eFUSE's AES key. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a6199ced282f260e182e7252a78354551"></a>
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          <td class="memname">#define XSK_EFUSEPL_ENABLE_RSA_AUTH&#160;&#160;&#160;FALSE</td>
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<p>If TRUE will enable RSA authentication of bitstream. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="ad14bece75c983e61cf1d11f5765c0d44"></a>
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          <td class="memname">#define XSK_EFUSEPL_FORCE_USE_FUSE_AES_ONLY&#160;&#160;&#160;FALSE</td>
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<p>If TRUE will force to use Secure boot with eFUSE key only. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a9a81580dacc2270f0daaed8aae100750"></a>
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          <td class="memname">#define XSK_EFUSEPL_GPIO_INPUT_CH&#160;&#160;&#160;(2)</td>
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<p>GPIO Channel for which TDO, Hardware module ready and end pins connected. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a82e4c58666c3f5f1f08b6588f468702d"></a>
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          <td class="memname">#define XSK_EFUSEPL_GPIO_OUTPUT_CH&#160;&#160;&#160;(1)</td>
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<p>GPIO Channel for which Hardware module Starte, TDI,. </p>
<ul>
<li>TMS and TCK pin connected </li>
</ul>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a9dc2b1efc06cb416f47f666cb928ce95"></a>
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          <td class="memname">#define XSK_EFUSEPL_PGM_SLR_CONFIG_ORDER_0&#160;&#160;&#160;FALSE</td>
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<p><h2>Definition of Zynq PL </h2>
</p>

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<a class="anchor" id="a13ad3c35e580ea044b38e632b35708ee"></a>
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          <td class="memname">#define XSK_EFUSEPL_PROGRAM_AES_KEY&#160;&#160;&#160;FALSE</td>
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<p>Following is the define to select if the user wants to select AES, User, RSA and RES keys for Ultrascale. </p>
<p>TRUE burns the AES key </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPL_PROGRAM_RSA_KEY_HASH&#160;&#160;&#160;FALSE</td>
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<p>TRUE burns the RSA hash. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPL_PROGRAM_USER_KEY&#160;&#160;&#160;FALSE</td>
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<p>TRUE burns the USER key. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPL_PROGRAM_USER_KEY_128BIT&#160;&#160;&#160;FALSE</td>
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<p>TRUE burns 128 bit USER key. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<p>TRUE read RSA Hash value. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a4ea026a1ab321b06be36cf1cb5192148">XilSKey_EfusePl_ReadnCheck()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPL_READ_USER_KEY&#160;&#160;&#160;FALSE</td>
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<p>TRUE read 32 bit USER key. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a4ea026a1ab321b06be36cf1cb5192148">XilSKey_EfusePl_ReadnCheck()</a>.</p>

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<p>TRUE reads 128 bit USER key. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a4ea026a1ab321b06be36cf1cb5192148">XilSKey_EfusePl_ReadnCheck()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPL_RSA_KEY_HASH_VALUE_CONFIG_ORDER_0&#160;&#160;&#160;&quot;000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000&quot;</td>
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<p>Following defines should be given only for Ultrascale the length of RSA string must be 96. </p>

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          <td class="memname">#define XSK_EFUSEPL_USER_KEY_128BIT_0_CONFIG_ORDER_0&#160;&#160;&#160;&quot;00000000&quot;	/* 31:0 */</td>
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<p>Following define should be given only for Ultrascale the total length of User 128-bit register is 128bit, to make it easier 128 bit register is broken into four 32 bit, single bit programming is also available. </p>

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          <td class="memname">#define XSK_EFUSEPS_DISABLE_DFT_JTAG&#160;&#160;&#160;FALSE</td>
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<p>DFT jtag Disable. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#ae591d283de7547921dda96ed1630dae9">XilSKey_EfusePs_InitData()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_DISABLE_DFT_MODE&#160;&#160;&#160;FALSE</td>
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<p>DFT mode Disable. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#ae591d283de7547921dda96ed1630dae9">XilSKey_EfusePs_InitData()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_ENABLE_ROM_128K_CRC&#160;&#160;&#160;FALSE</td>
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<p>Enable the ROM code 128K crc eFUSE Bit. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#ae591d283de7547921dda96ed1630dae9">XilSKey_EfusePs_InitData()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_ENABLE_RSA_AUTH&#160;&#160;&#160;FALSE</td>
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<p>Enable the RSA Authentication eFUSE Bit. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#ae591d283de7547921dda96ed1630dae9">XilSKey_EfusePs_InitData()</a>.</p>

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<p>Enabling this RsaKeyHashValue[64] is written to eFUSE array. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#ae591d283de7547921dda96ed1630dae9">XilSKey_EfusePs_InitData()</a>.</p>

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<p><h2>Similarly we can define PS eFUSE related data </h2>
</p>
<p>Enable the eFUSE Array write protection </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#ae591d283de7547921dda96ed1630dae9">XilSKey_EfusePs_InitData()</a>.</p>

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